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NCP362 USB Positive Overvoltage and Overcurrent Protection with TVS for VBUS and Low Capacitance ESD Diodes for Data
The NCP362 disconnects systems at its output when wrong VBUS operating conditions are detected at its input. The system is positive overvoltage protected up to +20 V, overcurrent protected up to 750 mA, and receives protection from ESD diodes for the high speed USB data and VBUS lines. Thanks to an integrated PMOS FET, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP362 is able to instantaneously disconnect the output from the input if the input voltage exceeds the overvoltage threshold OVLO. Thanks to an overcurrent protection, the integrated PMOS turns off when the charge current exceeds the current limit (see options in ordering information). The NCP362 provides a negative going flag (FLAG) output, which alerts the system that voltage, current or overtemperature faults have occurred. In addition, the device integrates ESD diodes for VBUS and data lines which are IEC61000-4-2, level 4 compliant. The ESD diodes for D+ and D- are compatible with high speed USB thanks to an ultra low capacitance of 0.5 pF.
Features
http://onsemi.com MARKING DIAGRAMS
UDFN10 CASE 517AV XXX M G XXXM G
= Specific Device Code = Date Code = Pb-Free Package
PIN CONNECTIONS
EN 1 GND 2 IN 3 VBUS TVS 4 GND 5 PAD1 GND 10 FLAG 9 OUT 8 GND 7 NC 6 NC
PAD2 GND
* * * * * * * * * * * * * * * * *
NCP362A Version (VBUS TVS + OVP/OCP) EN 1 GND 2 IN 3 NC 4 GND 5 PAD1 GND 10 FLAG 9 OUT 8 GND 7 D+ 6 D-
Overvoltage Protection up to 20 V Undervoltage and Overvoltage Lockout (UVLO/OVLO) Overcurrent Protection Transient Voltage Suppressor for VBUS Pin Ultra Low Capacitance ESD for Data Lines Alert FLAG Output and EN Enable Pin Thermal Shutdown Compliance to IEC61000-4-2 (Level 4) Compliance Machine Model and Human Body Model 10 Lead UDFN 2x2.5 mm Package This is a Pb-Free Device USB Devices Mobile Phones Peripheral Personal Digital Assistant MP3/MP4 Players TV and Set Top Boxes
PAD2 GND
NCP362B Version (D+/- ESD low cap + OVP/OCP)
EN 1 GND 2 IN 3 VBUS TVS 4 GND 5 PAD1 GND
10 FLAG 9 OUT 8 GND 7 D+ 6 D-
Applications
PAD2 GND
NCP362C Version (VBUS TVS + D+/- ESD low cap + OVP/OCP)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
Q
(c) Semiconductor Components Industries, LLC, 2009
March, 2009 - Rev. 0
1
Publication Order Number: NCP362/D
NCP362
USB Connector Bottom Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 VBUS D+ D- ID GND I limit >550 mA Soft start VIN/VBUS OUT Battery Charger System
VREF
Driver
OVLO UVLO Logic Thermal shutdown
VBUS TVS EN pin FLAG
GND
NCP362A
D+ D- USB Transciever
Figure 1. Typical Application Circuit with Wall Adapter / VBUS TVS Protection (NCP362A)
USB Connector Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 VBUS D+ D- ID GND I limit >550 mA Soft start VIN/VBUS OUT Battery Charger System
VREF
Driver
OVLO UVLO Logic Thermal shutdown
VBUS TVS D+ D- EN pin FLAG
GND
NCP362C
D+ D- USB Transciever
Figure 2. Typical Application Circuit with Full Integrated ESD for USB (NCP362C)
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NCP362
PIN FUNCTION DESCRIPTION
Pin No. 1 Name EN Type INPUT Description Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND or to a I/O pin. This pin does not have an impact on the fault detection. Ground Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. Cathode of the VBUS transient voltage suppressor diode. (NCP362A & NCP362C) This pin is not connected in the NCP362B Ground Cathode of the D- ESD diode. (NCP362B & NCP362C) This pin is not connected in the NCP362A Cathode of the D+ ESD diode. (NCP362B & NCP362C) This pin is not connected in the NCP362A Ground Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin. The two OUT pins must be hardwired to common supply. Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. Ground. Must be used for power dissipation. See PCB recommendations. Anode of the TVS and/or ESD diodes. Must be connected to GND.
2 3 4 5 6 7 8 9
GND IN VBUS TVS GND D- D+ GND OUT
POWER POWER INPUT POWER INPUT INPUT POWER OUTPUT
10
FLAG
OUTPUT
PAD1 PAD2
GND GND
POWER POWER
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NCP362
MAXIMUM RATINGS
Rating Minimum Voltage to GND (Pins IN, EN, OUT, FLAG) Maximum Voltage to GND (Pin IN) Maximum Voltage to GND (Pins EN, OUT, FLAG) Maximum DC Current from Vin to Vout (PMOS) (Note 1) Thermal Resistance, Junction-to-Air Operating Ambient Temperature Range Storage Temperature Range Junction Operating Temperature Human Body Model (HBM) (Note 2) Pins EN, IN, OUT, GND VBUS TVS Machine Model (MM) (Note 3) Pins EN, IN, OUT, GND VBUS TVS IEC 61000-4-2 Pin VBUS TVS Contact Air Pins D+ & D- Contact Air Forward Voltage @ 10 mA Pin VBUS TVS Pins D+ & D- Moisture Sensitivity MSL Vesd 30 30 10 15 1.1 1.0 Level 1 - kV kV kV kV V Symbol Vmin Vmaxin Vmax Imax RqJA TA Tstg TJ Value -0.3 21 7.0 600 280 -40 to +85 -65 to +150 150 2000 16000 V 200 400 Unit V V V mA C/W C C C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. With minimum PCB area. By decreasing RqJA, the current capability increases. See PCB recommendation page 9. 2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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NCP362
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (-40C < TA < +85C) and Vin = +5.0 V. Typical values are TA = +25C, unless otherwise noted.) Characteristic Input Voltage Range Undervoltage Lockout Threshold Uvervoltage Lockout Hysteresis Overvoltage Lockout Threshold Overvoltage Lockout Hysteresis Vin versus Vout Dopout Overcurrent Limit Supply Quiescent Current Standby Current Zero Gate Voltage Drain Current FLAG Output Low Voltage FLAG Leakage Current EN Voltage High EN Voltage Low EN Leakage Current TIMINGS Start Up Delay FLAG going up Delay Output Turn Off Time Alert Delay Disable Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis Capacitance (Note 7) Pin VBUS TVS Pins D+ & D- Clamping Voltage (Notes 5, 6, 7) Pin VBUS TVS Pins D+ & D- Working Peak Reverse Voltage (Note 7) Pin VBUS TVS Pins D+ & D- Maximum Reverse Leakage Current Breakdown Voltage (Note 4) Pin VBUS TVS Pins D+ & D- 4. 5. 6. 7. ton tstart toff tstop tdis Tsd Tsdhyst C 30 0.5 VC @ IPP = 5.9 A @ IPP = 1.0 A 0.9 V 23.7 9.8 V 12 5.0 IR VBR @ VRWM @ IT = 1.0 mA 1.0 mA V 13.5 5.4 From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9 From Vin > UVLO to FLAG = 1.2 V, See Fig 3 & 10 From Vin > OVLO to Vout 0.3 V, See Fig 4 & 11 Vin increasing from 5 V to 8 V at 3 V/ms. From Vin > OVLO to FLAG 0.4 V, See Fig 4 & 12 Vin increasing from 5 V to 8 V at 3 V/ms From EN 0.4 to 1.2V to Vout 0.3 V, See Fig 5 & 13 Vin = 4.75 V. 4.0 3.0 0.7 1.0 3.0 150 30 1.5 15 ms ms ms ms ms C C pF Symbol Vin UVLO UVLOhyst OVLO OVLOhyst Vdrop Ilim Idd Istd IDSS Volflag FLAGleak Vih Vil ENleak Vin = 5 V, I charge = 500 mA Vin = 5 V No Load, Vin = 5.25 V Vin = 5 V, EN = 1.2 V VDS = 20 V, VGS = 0 V Vin > OVLO Sink 1 mA on FLAG pin FLAG level = 5 V Vin from 3.3 V to 5.5 V Vin from 3.3 V to 5.5 V EN = 5.5 V or GND 170 1.2 0.55 5.0 550 Vin rises above OVLO threshold Vin falls below UVLO threshold Conditions Min 1.2 2.85 50 5.43 50 3.0 70 5.675 100 150 750 20 26 0.08 400 Typ Max 20 3.15 90 5.9 125 200 950 35 37 Unit V V mV V mV mV mA mA mA mA mV nA V V nA
ESD DIODES (TA = 25C, unless otherwise noted)
VRWM
VBR is measured with a pulse test current IT at an ambient temperature of 25C. Surge current waveform per Figure 28 in ESD paragraph. For test procedures see Figures 26 and 27: IEC61000-4-2 spec, diagram of ESD test setup and Application Note AND8307/D. ESD diode parameters are guaranteed by design.
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NCP362
ELECTRICAL CHARACTERISTICS
(TA = 25C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Max. Capacitance @VR = 0 and f = 1 MHz IPP VC VBR VRWM IR VF IT V IF I
*Additional VC, VRWM and VBR voltage can be available. Please contact your ON Semiconductor representative for availability. Uni-Directional TVS
Vin
UVLO ton
OVLO toff 0.3 V tstop 0.4 V
Vin - RDSon x I Vout
Vout
Figure 3. Start Up Sequence
Figure 4. Shutdown on Over Voltage Detection
EN
1.2 V tdis
EN
1.2 V OVLO
Vout Vin - RDS(on) x I FLAG
0.3 V
Vout
UVLO tstart
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
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NCP362
CONDITIONS IN OUT VIN > OVLO or VIN < UVLO
Voltage, Current and Thermal Detection
Figure 7.
CONDITIONS IN OUT UVLO < VIN < OVLO
Voltage, Current and Thermal Detection
Figure 8.
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NCP362
TYPICAL OPERATING CHARACTERISTICS
Figure 9. Start Up. Vin=Ch1, Vout=Ch2
Figure 10. FLAG Going Up Delay. Vin=Ch1, FL:AG=Ch3
Figure 11. Output Turn Off time. Vin=Ch1, Vout=Ch2
Figure 12. Alert Delay. Vout=Ch1, FLAG=Ch3
Figure 13. Disable Time. EN=Ch4, Vin=Ch1, Vout=Ch2
Figure 14. Thermal Shutdown. Vin=Ch1, Vout=Ch2, FLAG=Ch3
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NCP362
TYPICAL OPERATING CHARACTERISTICS
450 400 350 RDS(on) (mW) 300 250 200 150 100 50 0 -50 0 50 TEMPERATURE (C) 100 150 Vin = 5 V Vin = 3.6 V
Figure 15. RDS(on) vs. Temperature (Load = 500 mA)
SUPPLY QUIESCENT CURRENT (mA) OVERCURRENT THRESHOLD (mA) 180 160 140 120 100 80 60 40 20 0 1 3 5 7 9 11 13 15 17 19 21 -40C 25C 125C 900 880 860 840 820 800 780 760 740 720 -50
Figure 16. Output Short Circuit
Vin = 3.25 V Vin = 3.6 V Vin = 4.2 V Vin = 5 V Vin = 5.25 V
0
50 TEMPERATURE (C)
100
150
Vin, INPUT VOLTAGE (V)
Figure 17. Quiescent Current vs. Input Voltage
Figure 18. Overcurrent Protection Threshold vs. Temperature
900 OVERCURRENT THRESHOLD (mA) 880 860 840 820 800 780 760 740 720 3 3.5 4 -25C -40C 4.5 5 5.5 0C 85C 125C 25C
INPUT VOLTAGE (V)
Figure 19. Overcurrent Protection Threshold vs. Input Voltage http://onsemi.com
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NCP362
Figure 20. VBUS TVS Clamping Voltage Screenshot Positive 8 kV contact per IEC 61000-4-2
Figure 21. VBUS TVS Clamping Voltage Screenshot Negative 8 kV contact per IEC 61000-4-2
Figure 22. D+ & D- Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000-4-2
Figure 23. D+ & D- Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000-4-2
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NCP362
Operation
NCP362 provides overvoltage protection for positive voltage, up to 20 V. A PMOS FET protects the systems (i.e.: VBUS) connected on the Vout pin, against positive overvoltage. The Output follows the VBUS level until OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the device has a built-in undervoltage lock out (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is above 3.0 V nominal. The FLAG output is pulled to low as long as Vin does not reach UVLO threshold. This circuit has a 70 mV hysteresis to provide noise immunity to transient condition.
Vin (V) 20 V OVLO UVLO 0
is automatically turned off (5 ms) if the charge current exceeds Ilim. NCP362 goes into turn on and turn off mode as long as defect is present. The internal ton delay (4 ms typical) allows limiting thermal dissipation. The Flag pin goes to low level when an overcurrent fault appears. That allows the microcontroller to count defect events and turns off the PMOS with EN pin.
Vout
Ilimit
I
t
toff Overcurrent
ton
Retrieve normal operation
t
Vout OVLO UVLO 0
Figure 25. Overcurrent Event Example FLAG Output
Figure 24. Output Characteristic vs. Vin Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from overvoltage, the device has a built-in overvoltage lock out (OVLO) circuit. During overvoltage condition, the output remains disabled until the input voltage exceeds 6.0 V. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a 100 mV hysteresis to provide noise immunity to transient conditions.
Overcurrent Protection (OCP)
NCP362 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon as: 1.2 V < Vin < UVLO, Vin > OVLO, Icharge > Ilimit, TJ > 150C. When NCP362 recovers normal condition, FLAG is held high. The pin is an open drain output, thus a pull up resistor (typically 1 MW - Minimum 10 kW) must be provided to VCC. FLAG pin is an open drain output.
EN Input
To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault.
Internal PMOS FET
The NCP362 integrates overcurrent protection to prevent system/battery overload or defect. The current limit threshold is internally set at 750 mA. This value can be changed from 150 mA to 750 mA by a metal tweak, please contact your ON Semiconductor representative for availability. During current fault, the internal PMOS FET
The NCP362 includes an internal PMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDS(on), during normal operation, will create low losses on Vout pin, characterized by Vin versus Vout dropout.
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NCP362
IEC 61000-4-2 Spec.
Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000-4-2 Waveform Ipeak 100% 90%
Level 1 2 3 4
Figure 26. IEC61000-4-2 Spec
ESD Gun
TVS
Oscilloscope
50 W Cable
50 W
Figure 27. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D - Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger
100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.
PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms
40 t, TIME (ms)
60
80
Figure 28. 8 X 20 ms Pulse Waveform
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NCP362
PCB Recommendations
The NCP362 integrates a 500 mA rated PMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The UDFN PAD1 must be connected to ground plane to increase the heat transfer if necessary from an application standpoint. Of course, in any case, this pad shall be not connected to any other potential. By increasing PCB area, the RqJA of the package can be decreased, allowing higher charge current to fill the battery. Taking into account that internal bondings (wires between package and silicon) can handle up to 1 A (higher than thermal capability), the following calculation shows
310 290 270 qJA (C/W) 250 230 210 190 175 2 oz C.F. 1 oz C.F.
two different example of current capability, depending on PCB area: * With 280C/W (without PCB area), allowing DC current is 500 mA * With 210C/W (200 mm2), the charge DC current allows with a 85C ambient temperature is: I = (TJ-TA)/(RqJA x RDSON) I = 800 mA In every case, we recommend to make thermal measurement on final application board to make sure of the final Thermal Resistance.
1 oz Sim 2 oz Sim
150 0 25 50 75 100 125 150 175 200 225 250 275 300 325350 COPPER HEAT SPREADING AREA (mm2)
Figure 29.
Top View
Bottom View
Figure 30. Demo Board Layout
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NCP362
TP3 Vcc
Vcc
1
R2 TP1 VBUS IN J5 1 2 3 4 5 6 7 8 9 10 11 TP2 VBUS TVS U1 1 2 C1 1F S1 1 STRAP2 6 7 R3 10k 3 4 In VBus Out NCP362 /Flag D- D+ GND GND GND GND GND 1 TP4 /FLAG 9 1 10k
R1 10k 1 2 3
J4
HEADER 3
J2 1 2 3 4 5 6
TP5 /EN
C2 1F
10 1
/EN
1 USB OUT
1
HEADER 11
TP6 ID
1
J3 GND
2
Figure 31. Demo Board Schematic
Bill of Material
Designation R1, R2 C1, C2 NCP362 GND Jumper EN, FLAG, IN, VBUS, ID, Vcc USB Input Connector USB Output Connector Hirose UX60-MB-5S AU Y1006 R Murata - GRM188R61E105KA12D ON Semiconductor WM8083-ND Jumper Ground 1mm pitch 10.16 mm SMB R 114 665 PCB Plated Gold 5 pins USB mini 4 pins USB A Manufacturer Specification 10k - CMS0805 1% 1 mF, 25 V, X5R, CM0805
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2 5 8 11 12
NCP362
ORDERING INFORMATION
Device NCP362AMUTBG NCP362BMUTBG NCP362CMUTBG Marking ADA ADG ADC Package UDFN10 (Pb-Free) UDFN10 (Pb-Free) UDFN10 (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP362 can be available in several undervoltage, overvoltage, overcurrent and clamping voltage versions. Part number is designated as follows:
NCP362xxxMUxxTBG
abc Code a de f g Contents ESD diode options A: TVS diode on pin 4 B: ESD diodes on pins 6 & 7 C: Option A & B TVS Pin 4 VRWM voltage -: 12 V ESD Pin 6 & 7 VRWM voltage -: 5 V Overcurrent Typical Threshold -: 750 mA UVLO Typical Threshold -: 3.00 V OVLO Typical Threshold -: 5.675 V Tape & Reel Type B: = 3000 Pb-Free
b c d e f g
NOTE: Please contact your ON Semiconductor representative for availability of additional options.
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NCP362
PACKAGE DIMENSIONS
UDFN10 2x2.5, 0.5P CASE 517AV-01 ISSUE O
D AB L1 L L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 D3 E E2 e F K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 2.50 BSC 1.35 1.55 0.30 0.50 2.00 BSC 0.95 1.15 0.50 BSC 1.08 BSC 0.20 --0.20 0.30 --0.15
2X
0.15 C
2X
0.15 C
DETAIL B
0.10 C 0.08 C
NOTE 4
A3
A A1
A1 SIDE VIEW B F
1 5
C
SEATING PLANE
0.10 C A
DETAIL A 10X
10X
D2
b 0.10 C A 0.05 C
B
L
NOTE 3
E2 0.10 C A K
10 6
B
PACKAGE OUTLINE
e F
D3
0.10 C A BOTTOM VIEW
B
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
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EEE CCC CCC
10X
II II
PIN ONE REFERENCE
E
OPTIONAL CONSTRUCTIONS
DETAIL A
EXPOSED Cu
MOLD CMPD
TOP VIEW
A3
OPTIONAL CONSTRUCTION
DETAIL B
SOLDERING FOOTPRINT*
1.55 1.13 0.35
10X
0.45 1.15 2.30
1 0.50 PITCH
0.50 1.13
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NCP362/D

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